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VENKATESA RAJA BALASUBRAMANIAN

Email:
Contact: 91 94423 40960
Coimbatore

Working as a product development lead in developing advanced communication and internet technologies and their implementation.

Semiconductors, Wireless/Wire line, Signal processing and Software engineering

Professional summary:

Senior Consultant, Product development: Semiconductors, Telecommunications and Software
Hands on experience and know-how of networking and communication systems/protocols such as WCDMA, SONET, OSPF, MPLS, L2/L3 switches.
Research future directions of technology migrations, in depth analysis of current and future generation products.
Currently involved in product definition, development and entrepreneurial activities related to technology advancement.
Research papers on DSP and communication algorithms performance analysis on processors and ASIC’s.
Developmental experience in analog/digital/RF systems and circuits for various products
ASIC front end developmental expertise for communication framers and network devices
Analog circuit design include ADC, DAC, op-amp circuits, RF transceiver modeling and design.
Leading technology developmental activities with an organization “Technovators” to promote value added products and services to nurture innovation

Work Experience:
Full time positions with Cypress Semiconductors, Sun Microsystems, Intel Corp, Altera Corp, Tag Array Corp

Technical Lead, Product development/Consulting lead
ADC Corp Coimbatore, India Mar 2007 – Present

Strategic research, developmental activities of products, services and solutions in some of the domain spheres, specifically advanced communication and internet technologies, solutions and their implementation in silicon. The company is in early startup mode.
Projects include software and hardware development for various systems and applications.
Low power sensor networks, Telemetric bio medical signal processing, Network Security.

Senior IC Architect
TagArray Los Altos, CA Nov 2007 – Feb 2008
Developed system/architecture design for RFID device that involved base band, MAC and power management for the complete transceiver.

Product Engineer
Altera Corp San Jose, CA 2007-2007

Logic design, timing closure and synthesis of at speed BIST for characterizing SRAM on FPGA. BIST for characterizing different flavors of SRAM dual port memory, supporting several modes of operation. Product roll-out with pre-silicon development.

Design Engineer
Intel Corp Folsom, CA 2005-2006

Design of dual port/compiler based RAMs. SRAM design of datapath, control path timing, statistical simulations, functional verification. Memory modeling, race checks, timing closure of 8T SRAM design. Datapath synthesis of adders, multipliers, simulator porting and enhancements related to circuit technology migration, productivity improvement and future usage.

MTS Hardware Engineer
Sun Microsystems Sunnyvale, CA 2005-2006

SRAM design, activities involved include physical design validation of core RAM blocks for usage in processor. Activities were DFT and physical design aspects.

Design Engineer
Cypress Semiconductor San Jose, CA 2003-2005

Block ownership of periphery blocks, timing closure, race checks and optimization, physical design, RTL level validation on test chip, functional issues, memory modeling and debugging. Switch level behavioral modeling of SRAM circuits, for simulation enhancement, logic validation of synchronous & asynchronous dual port memory. Feasibility analysis of power models, logic plan/validation of SRAM, yield analysis of embedding SRAMs in ASICs.
Architecture and microinstruction level performance analysis of TigerSharc and Blackfin DSP processors to evaluate dual port memory usage. This involved analyzing the cache, main memory accesses, locking, hits, misses and blocking encountered by single and dual processor communication.
Logic modeling of metro-link device, SONET framer, modeling and logic validation of transceiver. Block requirement study, modeling and test bench development for verification of TX and RX.

Other projects: Viterbi codec, equalizers, diversity receivers, wireless channel modeling and simulation, audio amplifiers, op-amp circuits, Nyquist rate A/D converters, OFDM transceiver modeling, signal estimators, WCDMA 3G/4G algorithms and transceivers.
Tools: Verilog, C, C++, Java, Cadence circuit design suites, Synthesis, Matlab, Synopsys DC/PC, Spice

Others:
Research papers on DSP algorithms and performance analysis on processors, communication system algorithms and performance on ASIC’s.
Data structures & algorithms, network protocols, communication systems and Integrated circuits.

Education:
Master of Science, Electrical Engineering 2000-2002 GPA 3.82
Arizona State University, Tempe
Project: Low power, high speed design of a rate 1/3 Viterbi codec
Advisor: Dr. Tolga Duman

Bachelor of Science in Electronics & Communications Engineering 1996-2000 GPA 3.8
PSG College of Technology, Coimbatore, India
Project: PCI Bus transactions simulation
Advisor: Dr. S.Jayaraman

Research Intern Center of Electronic Design and Technology, Indian Institute of Science, India
1999-1999
Helped in the development of disk quota enforcement to enforce access control in the servers.
Activities:
Graduate Scholarship award for excellent academic performance at Arizona State University
Distinction honor at PSG College of Technology
Award of honor of “The Best Outgoing student” and distinction award from the “Government of India”
Member of IEEE, TIE, SPIE
Active participant in soccer, athletic and sports events

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