Project Detail

IC Design - Verilog assignment

IC Design - Verilog assignment is project number 353769
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Status:

Selected Providers: qasimmaqbool

Budget: $30-250

Created: 12/06/2008 at 0:54 EST

Bid Count: 7

Average Bid:
$ 165

12/11/2008 at 0:54 EST

Project Creator: astroboy1983
Employer Rating: 10/10 10/10 10/10 10/10 10/10 10/10 10/10 10/10 10/10 10/10 (1 reviews)

Description

please check attachment for detail

Additional information submitted:

12/06/2008 at 0:56 EST:
Simple Car Park Controller

Additional files submitted:
cpc.pdf

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Job Type

Engineering

See more: assignment, design, verilog

Messages Posted:0

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PMB

200

7 days

12-06-2008 03:54 EST

9.75/10 9.75/10 9.75/10 9.75/10 9.75/10 9.75/10 9.75/10 9.75/10 9.75/10 9.75/10
(4 reviews)

please check your PMB

qasimmaqbool

100

7 days

12-07-2008 05:40 EST

10/10 10/10 10/10 10/10 10/10 10/10 10/10 10/10 10/10 10/10
(1 reviews)

Please see PMB.

WaheedRamzan

100

15 days

12-06-2008 04:08 EST

(No Feedback Yet)

Please see PMB

hdlveca

200

10 days

12-06-2008 07:33 EST

(No Feedback Yet)

Please see the PMB.

srajita

200

10 days

12-06-2008 09:14 EST

(No Feedback Yet)

Kindly see PMB

huzefaf

165

11 days

12-06-2008 09:51 EST

(No Feedback Yet)

Is it OK if the Functional Verification is done using ModelSim. Also could you please clarify what is the HKU IC design flow?

contact2web

190

7 days

12-07-2008 00:43 EST

(No Feedback Yet)

Please see PMB

Bid on this Project

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